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MTS - Library Design/standard Cell
Maxim India Integrated Circuit Design Pvt Ltd.
Electronics , Research And Development
Bengaluru,Karnataka Post Date May, 08 2019 Age Range 28 To 32 Annual CTC ( 4 - 8 Lacs ) ( Experience: 4-8 Years )Overview
Maxims Electronic Design Automation (EDA) group is seeking a Library Engineer to QA/develop logic IPs (standard cells, IOs and memories) to support digital and mixed-signal SOC designs at various technology nodes.
Skills
- Synopsys Verilog Communication Skills Circuit Designing Electrical Engineering Verbal Communication
Job Description
- Library and memory QA for digital, analog and mixed-signal design and PnR flows. Library QA methodology development and execution. IO cell characterization and model generation Debugging library, memory and design issues. Programming and scripting for flow and procedure automation. *Minimum Qualifications 3+ years of experience in library QA and development, Master's degree in Electrical Engineering or equivalent Familiar with logic cell development and verification. Strong Knowledge with circuit design and transistor-level/gate-level simulations Experience with Cadence and Synopsys design, layout, and simulation tools Familiar with behavior (Verilog) languages Strong experience with Perl and/or Skill scripting languages Strong written and verbal communication skills.