Job Details

Overview

he candidate will be working for SoC design team which develops embedded multiprocessing SoC. The state-of-the art SoC works as highly configurable, multiple processing system in conjunction with programmable logic. The design activities includes micro-architecture, RTL design, quality checks (Lint/CDC), and SoC integration. The SoC integration will also have synthesis constraint development and timing closure activities thru sign-off tools like DC/PT. As part of design team, the candidate will own design feature/IP and will support for validation of the IP/System or system SW working with respective teams. The ideal candidate will have decent micro-architecture knowledge for new IP or subsystem development

Skills

• MS/M.Sc(Science) - Any Specialization, Electronics, M.Tech - Any Specialization, Electronics/Telecommunication

Job Description

• MS / M-Tech in VLSI or similar stream with minimum 7+ yrs of relevant experience in RTL design/SoC Integration Expertise in some or all protocols: SD host 3.0, Ethernet, ONFI 3.1 NAND, video encoder/decoder Work experience in ARM and AXI bus based system, knowledge of memory controller required Knowledge in Low power design methodology is plus Proficient in static timing analysis (primetime based). Have at least closed Prime time based timing closure for at least one SoC Can write sdc/tcl for DC/Primetime(PT) tool for STA analysis, should be able to create synthesis constraints based on design requirements Have good knowledge in scripting language like perl/python (optional) Should have knowledge in clock-domain crossing(CDC, Spyglass, 0in), Linting(Spyglass) and other RTL quality checks Team player with ability to work w/ multisite and local teams